Many integrated circuits have signal lanes that support transmission and/or receipt of data signals. Those signal lanes can include circuitry (e.g., serializer/deserializer, or SERDES, circuits) to prepare bit data for transmission and/or to recover bit data after receipt. Noise sources (e.g., power supplies) and other non-idealities can produce jitter (e.g., random jitter, or RJ) on clocking signals (e.g., on the output of the phase-locked loop (PLL)). For example, a PLL tends to be a highly sensitive circuit that is highly susceptible to internal and/or external noise, which can cause jitter. For high-speed SERDES links, jitter on the PLL output (e.g., primarily deterministic and random jitter) can appreciably affect the link performance, particularly where the PLL is the primary clock source for both the transmitter and receiver circuits of the SERDES. For example, jitter within a SERDES can degrade jitter generation on the transmitter side and can degrade jitter tolerance on the receiver side. The susceptibility of external noise and suppression of internal noise can be a function of PLL loop parameters (e.g., parameters of transmit and/or receiver filters, equalizers, etc.), and the performance can vary appreciably due to different process characteristics, voltages, temperatures, and/or other characteristics, even with the same loop parameter settings. Performance impacts can be further exacerbated when a single chip contains many lanes, each adding to process variations and ultimately degrading yield. For example, some modern processors include hundreds of lanes with tens of PLLs. Conventional approaches to addressing jitter performance in high-speed SERDES links tend to focus on designing high-accuracy PLLs across different corners, but such approaches can involve tremendous effort and can become impractical as the link speed and number of lanes increase.